Modern computer systems include a variety of components that communication with each other. For example, a processor communicates with a memory such as a registered dual inline memory module (DIMM) including a register device having configuration registers and multiple DRAM devices each including mode registers, via a memory controller. For a registered DIMM, all commands must pass through the register device on the DIMM, before going to the DRAM devices. Oftentimes, commands are sent to the DRAM from the processor through the memory controller. Such commands may be to write and read data. Additional commands are used to control various operation modes of the DRAM devices. Such commands are referred to as mode register set (MRS) commands. During operation, numerous such commands may be sent to a memory to control various modes, initiate status updates and to perform other operations.
Typically, to program a mode register in a DRAM device, a user must ensure that the register device has address inversion disabled and is in a slow timing mode. In contrast, during normal memory operations, the register device generally operates with a faster timing and with address inversion enabled, as these modes improve performance and reduce power consumption. To initiate such changes, a relatively long time is needed for the memory controller to pause normal operation, perform register configuration cycles, send the MRS commands, then again perform register configuration cycles, and then finally resume normal operation.
As described above, when programming MRS commands, address inversion has to be turned off (which is the single largest contributor to controlling simultaneous switching outputs (SSO) and its power impacts). The longer the system has address inversion turned off, the harder it is to optimize the power delivery system to take advantage of such inversion.